The invention relates to a circuit arrangement for generating an n-bit output pointer, in particular for a FIFO-based read latency counter having an adjustable read latency in a semiconductor memory. The invention also relates to a semiconductor memory and to a method for adjusting a read latency.
There is increasingly a need, in modern computer and software applications, to process ever larger volumes of data in an ever shorter period of time. Large-scale integrated memories, for example synchronous dynamic random access memories (S-DRAM memories), are used to store the data. S-DRAMs are standard memory modules which comprise large-scale integrated transistors and capacitors and allow the memory to be accessed without additional waiting cycles.
FIG. 1 of the drawing shows part of the read path of a S-DRAM 1, as is illustrated in German patent No. 102 10 726 B4, in particular in FIG. 1 there. A sense amplifier 3 and an internal data bus 4 are used to read out read data from the memory cell array 2 in clocked fashion using an internal clock signal CLK. A data buffer FIFO 5 is arranged in the read path in order to synchronously output data. The read data which are buffer-stored there are read out from the FIFO 5 using an OCD driver 6 (Off Chip Driver) and are supplied, via an external data bus 7, to a microcontroller, for example, for further processing. The FIFO 5 is driven by the sense amplifier 3 using a read pointer INP and by a read latency generator 8 using an output pointer OUTP that acts as a time-delayed data enable signal.
Signal delays play a significant role in a read access operation. On the one hand, a read-out time tAA is needed to read out the read data RDint from the memory cell array 2 and provide them for the OCD driver 6. A further signal delay results from the propagation time tDP of the read data RDout through the OCD driver 6. The so-called read latency ΔT is defined on the basis of the known signal delays tAA, tDP, said read latency denoting the period of time that is at least needed to read out read data from the memory cell array 2 and provide them at the output of the OCD driver 6 taking into account the signal delays tAA, tDP. The read latency ΔT is generated by the read latency generator 8 which correspondingly shifts the output pointer OUTP relative to the input pointer INP of the FIFO 5 by a minimum number n of clock pulses that corresponds to the read latency ΔT.
These n clock pulses of the read latency ΔT are counted using a read latency counter 8 which is specifically provided for this purpose and, in a corresponding manner, shifts the output counter OUTP relative to the input counter INP by a number n of clock pulses of the clock signal CLK. When implementing a read latency counter, use is usually made of a FIFO-based concept in which the chip-internal read signal RDint is shifted, under the control of the read latency generator 8, by the programmed read latency ΔT and is changed to the domain of the external clock signal DLL-CLK. FIG. 2 of the drawing uses a block diagram to show a FIFO 9 having four individual FIFO cells 9a and thus a FIFO depth of 4. The clock domain is shifted by, for example, the input pointer INP0 opening the cell “0” of the data buffer FIFO, so that the internal data signal RDint is consequently read in there. At the same time, the output counter OUTP1, for example, is active. This results in the internal data signal RDint only being read out from the cell “0” three clock pulses later (see FIG. 3A) assuming that each input pointer INP0-INP3 and each output pointer OUTP0-OUTP3 are respectively alternately active in succession for the duration of one clock pulse.
In modern semiconductor memories, there is increasingly a need to be able to adjust not only an individual read latency ΔT but different read latencies ΔT so that the semiconductor memory can also be operated in different operating modes. In order to then change a read latency ΔT that has been set, the output pointer must be shifted relative to the input pointer. If, in the example described above, the output pointer OUTP2 for the FIFO cell “2”, for example, were active rather than the output pointer OUTP1 for the FIFO cell “1”, the read data stored in the data buffer FIFO would be read out from the latter one clock pulse earlier, thus corresponding to a read latency that has been reduced by 1.
FIG. 3 shows a block diagram of one implementation of a programmable read latency ΔT for explaining the general problem. In this case, provision is made of a 4-bit ring counter which is denoted using reference symbol 10 and thus has four counter stages 10a and provides a 4-bit counter reading signal CNT0-CNT3 in accordance with the counter reading.
n multiplexer stages 11 are also required for an n-bit output pointer, each multiplexer stage generating one bit of the output pointer OUTP at the output. The inputs of the multiplexer stages 11 are each connected to the outputs of the ring counter 10 in a different order. A multiplexer control signal 11a can be used to select the respective read latency, which is desired or is to be adjusted and is reflected in the output pointer OUTP, by supplying the same control signal 11a to each multiplexer 11 for the purpose of selecting the respective same multiplexer input. The counter reading of the ring counter 10 is respectively injected in a particular order into the inputs of the multiplexer stages 11.
The problem with this implementation is, on the one hand, that, particularly in the case of a multiplicity of read latencies ΔT to be programmed, a corresponding multiplicity of input connections of the multiplexers 11 must be provided. On the other hand, the ring counter 10 also thus becomes very complicated in terms of circuitry since it must have a number of counter stages 10a corresponding to the bit width of the output pointer OUTP. In the case of a multiplicity of such counter stages 10a, the feedback line 10b of the ring counter 10 becomes very long, which results in a diminished performance of the ring counter on account of the signal propagation times. In particular, the ring counter 10 is then increasingly slow. In addition, an ever larger number of multiplexer stages is required, which results in an ever higher load being associated with each bit CNT0-CNT3 of the counter reading signal or the respective output. Correct functionality thus becomes increasingly difficult at high operating frequencies for reading out read data.
This problem arises, in particular, in the case of very large read latencies and very long counter and multiplexer lines, which may result, on the one hand, in longer propagation times of the signals on these lines and, on the other hand, in parasitic capacitances. These are undesirable influences which need to be avoided, in particular when operating large-scale integrated semiconductor memories in the high MHz range and as of the GHz range, since the information stored in the semiconductor memory thus cannot be read out in a defined manner or can be read out only with a considerable amount of additional complexity and/or with the acceptance of data losses during the read-out operation. This is a state which understandably needs to be avoided.